1. Field of the Invention
The present invention involves fabrication of semiconductor devices using Silicon-on-Insulator (SOI) technology. More specifically the invention is directed to the use of the SOI Buried Oxide (BOX) layer as an integral component of electronic devices and circuits.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology has emerged as an electronic fabrication technique that improves characteristics such as latchup and speed, although typically at higher manufacturing cost. The term SOI typically describes structures where devices are fabricated in single-crystal Si layers formed over an insulating film or substrate.
FIGS. 11A and 11B show a typical conventional SOI structure, where a thin silicon device layer 110 formed on an insulator 111 is supported over substrate 112. For current technology the substrate is most commonly silicon and the insulator is most commonly silicon dioxide. Devices 113 are formed in device layer 110 and interconnected by surface conductors 114. The conventional SOI structure is predominantly created by one of two techniques.
The first process, known as SIMOX (Separation by IMplanted OXygen), consists of implantation of oxygen into an Si substrate at a prescribed depth and heating it to form a continuous layer of SiO2. The SIMOX process requires only a single wafer. The alternate process, shown in greater detail later, is commonly referred to as xe2x80x9cBonded SOIxe2x80x9d and starts with two wafers, preferably with at least one having an oxide surface. The first wafer is the carrier wafer which is joined together with the second wafer, and the second wafer is xe2x80x9cthinnedxe2x80x9d to leave a layer of silicon bonded onto the carrier wafer, separated by an insulator layer.
Both of the techniques have experienced many variations and enhancements over the years for improvement of yield and lower cost and to achieve desirable device layer quality for uniformity and defects. An important characteristic of conventional SOI that is obvious from FIG. 11B is that the insulator layer 111 is used primarily for isolating the silicon device layer 110 with its active devices 113 from the silicon substrate 112. Thus, the conventional wisdom forms devices on the device layer 110 on only one side of the insulator layer 111.
The problem with this approach is that, although devices and interconnects are formed similar to conventional substrates, SOI techniques introduce newer problems such as floating body effects. Additionally, conventional SOI structure takes up considerably more chip xe2x80x9creal estatexe2x80x9d than required in corresponding non-SOI structure, since floating body effects which not an issue with conventional substrates require additional connections to the channel regions. There are also added process steps to provide ground interconnections to the substrate. More important, the conventional approach fails to recognize that the insulator layer could provide more functionality than merely separating predetermined groups of devices from the substrate.
The inventors have recognized that the SOI insulator layer, or BOX (Buried OXide), can be an integral part of a specific device, and further, even circuits can be advantageously built around this innovative approach. That is to say, the BOX can be considered more than a mere passive isolation mechanism separating layers of devices. It can become an integral component even of an entire circuit. As will be demonstrated, by adopting this innovative approach, a whole new possibility opens up for SOI technology that provides improved device density and speed and fewer conductor interconnects between devices.
Therefore, an object of the invention is to teach methods in which the SOI insulator (BOX) is used as a building component at the device level.
Another object of the invention is to teach methods in which the BOX serves as a building component at the circuit level.
Another object of the present invention is to teach a method in which the BOX is used for functions other than simple isolation between layers of devices.
Another object of the present invention is to teach a method in which the BOX is even used for functions other than isolation even within a single device.
Another object of the present invention is to improve electronic device density on SOI chips.
Another object of the present invention is to reduce the number of conductor interconnects between devices on SOI chips.
Another object of the present invention is to reduce parasitics and increase speed on SOI chips.
Another object of the present invention is to teach methods for forming features in the substrate prior to the formation of SOI structure.
Another object of the present invention is to teach methods to form improved FET devices on SOI.
A still further object of the invention is demonstrate applications that take advantage of the above methods.
Yet another object of the invention is to demonstrate the above goals and techniques using established silicon manufacturing processes and equipment.
To achieve the above objects according to a first aspect of the invention, a method and structure is disclosed of fabricating an electronic device using an SOI technique resulting in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, where the first component and the second component are on opposite sides of the buried oxide layer so that the buried oxide layer performs a function within the electronic device.
According to a second aspect of the invention, a method is disclosed of fabricating an electronic circuit using an SOI technique, said SOI technique resulting in formation of at least one buried oxide layer, the electronic circuit comprising a plurality of interconnected electronic devices, each electronic device comprising a respective plurality of components. The method includes fabricating a predetermined first set of respective plurality of components to be on a first side of the buried oxide layer and fabricating a predetermined second set of respective plurality of components to be on a second side of the buried oxide layer, where the second side is the opposite side of the first side, and where the buried oxide layer performs a function integral to the functioning of at least one of the electronic devices.
According to a third aspect of the invention, a method is disclosed of SOI fabrication in which a buried oxide layer is formed, where the method includes forming a first set of device components to be on a first side of the buried oxide layer and forming a second set of device components to be on the side opposite the first side, where the buried oxide layer performs a function integral to the functioning of at least one device comprised of components from the first set of components and components from the second set of components.
According to a fourth aspect of the invention, a method and structure are disclosed of fabricating a DRAM cell using an an SOI technique on a substrate, where the SOI technique results in formation of at least one buried oxide layer. The method includes forming a buried capacitor beneath the buried oxide layer, subsequently forming an FET source and drain regions on top of the buried oxide layer, and interconnecting the capacitor to one of the source region or drain region with a via penetrating the buried oxide layer, where the via is a conductive material.
According to a fifth aspect of the invention, a method and structure are disclosed of fabricating a DRAM cell using an SOI technique, where the SOI technique results in formation of at least one buried oxide (BOX) layer, whereby a capacitor for the DRAM cell is formed by a process including forming a buried electrode in a substrate, wherein the buried electrode serves as a lower capacitor charge plate and forming a diffusion link between the diffusion region of a transistor located on the upper side of the BOX and a region to comprise an upper charge plate of the capacitor, where the upper charged plate of the capacitor is formed on the upper side of the BOX when impressing a bias voltage on the buried electrode.
According to a sixth aspect of the invention, a method and structure are disclosed of fabricating an electronic circuit having a plurality of electronic devices using an SOI technique, the SOI technique resulting in formation of at least one buried oxide layer. The method includes forming an interconnector of conductive material to interconnect at least two of said plurality of electronic devices, the interconnector at least partially enclosed by said buried oxide.
According to a seventh aspect of the invention, a method and structure are disclosed of fabricating a dynamic two-phase shift register. The method includes forming a buried oxide layer using an SOI technique, forming a plurality of FET transistors to be in a device layer above the buried oxide layer, forming a first clock signal conductor on top of the device layer, and forming a second clock signal conductor below the device layer, the second clock signal conductor at least partially enclosed by the buried layer.
According to an eighth aspect of the invention, a method and structure are disclosed of fabricating a CMOS circuit. The method includes forming a buried oxide layer using an SOI technique and forming a plurality of FET transistors to be in a device layer above the buried oxide layer, wherein at least two of the FET transistors share a common diffusion region, thereby electrically interconnecting the two FET transistors without using a separate interconnecting conductive material.
According to a ninth aspect of the invention, a method and structure are disclosed of fabricating a FET using an SOI technique, the SOI technique resulting in formation of at least one buried oxide layer. The method includes forming a first gate beneath the buried oxide layer and forming a second gate on top of the buried oxide layer.
According to a tenth aspect of the invention, a structure is disclosed of an electronic device including at least one SOI buried oxide layer, where the at least one buried oxide layer performs a function integral to the device.
According to an eleventh aspect of the invention, a structure is disclosed of an electronic device comprising at least one SOI buried oxide layer, where the at least one SOI buried oxide layer becomes a structural element integral to the device.
According to a twelfth aspect of the invention, a structure is disclosed of an electronic circuit comprising a plurality of interconnected devices, the circuit mounted on a wafer having at least one SOI buried oxide layer, wherein the at least one SOI buried oxide layer is a functional element integral to at least one of the devices.
According to a thirteenth aspect of the invention, a structure is disclosed of an electronic circuit comprising a plurality of interconnected devices, the circuit mounted on a wafer having at least one SOI buried oxide layer, where the at least one SOI buried oxide layer comprises a structural element integral to at least one of the devices.
According to a fourteenth aspect of the invention, a structure is disclosed of an electronic circuit comprising a plurality of interconnected devices, the circuit mounted on a wafer having at least one SOI buried oxide layer, where the two adjacent devices share at least one device component, thereby electrically interconnecting the two devices without an interconnecting conductor, and where the SOI buried oxide layer serves to isolate components of the two interconnected devices other than the shared component.
According to a fifthteenth aspect of the invention, a method is disclosed of SOI fabrication wherein a buried oxide layer is formed. The method includes forming a first set of device components to be on a first side of the buried oxide layer and forming a second set of device components to be on the side opposite, where the buried oxide layer is used for an active functioning of at least one buried device.